Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits

Journals Menu

Follow SCIRP

ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.org/journal/cs
E-mail: cs@scirp.org

Citations h5-index & Ranking*

"Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits"
written by Abdoul Rjoub, Almotasem Bellah Alajlouni, Hassan Almanasrah,
published by Circuits and Systems, Vol.4 No.2, 2013

has been cited by the following article(s):

[1]	Development of Static Timing Analysis Tool in Perl
	2020

[2]	Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing
	2019

[3]	Research of timing graph traversal algorithm in static timing analysis based on FPGA
	2017

Follow SCIRP