Future Semiconductor Devices for Multi-Valued Logic Circuit Design

ISSN Print: 2153-117X
ISSN Online: 2153-1188
www.scirp.org/journal/msa
E-mail: msa@scirp.org

"Future Semiconductor Devices for Multi-Valued Logic Circuit Design"
written by Supriya Karmakar, Faquir C. Jain,
published by Materials Sciences and Applications, Vol.3 No.11, 2012

has been cited by the following article(s):

[1]	Recent Advances on Multivalued Logic Gates: A Materials Perspective
	2021

[2]	Ge-based reconfigurable transistors: a platform enabling negative differential resistance
	2021

[3]	Phase-Engineered Molybdenum Telluride/Black Phosphorus Van der Waals Heterojunctions for Tunable Multivalued Logic
	2020

[4]	Multivalued logic implementation using Quantum dot gate non-volatile memory
	2019

[5]	Gate Quantum Capacitance Effects in Nanoscale Transistors
	2019

[6]	Dual Quantum Dot Superlattice
	International Journal of High Speed Electronics and Systems, 2018

[7]	Design of Multi-state DRAM Using Quantum Dot Gate Non-volatile Memory (QDNVM)
	Silicon, 2018

[8]	Optimizing Fabrication and Modeling of Quantum Dot Superlattice for FETs and Nonvolatile Memories
	2017

[9]	Modeling of Multi-State Spatial Wavefunction Switched (SWS) FETs for Logic Gates and Memories
	2017

[10]	A New Approach for Multi-Valued Computing Using Machine Learning
	2017

[11]	Ternary static random access memory using quantum dot gate field-effect transistor
	Micro & Nano Letters, IET, 2015

[12]	Ternary static random access memory using quantum dot gate field‐effect transistor
	Micro & Nano Letters, 2015

[13]	A novel tri-state device implemented with a metal gated QCA
	Circuits and Systems (LASCAS), 2014 IEEE 5th Latin American Symposium on. IEEE, 2014

[1]	Phase-Engineered Molybdenum Telluride/Black Phosphorus Van der Waals Heterojunctions for Tunable Multivalued Logic ACS Applied Materials & Interfaces, 2020 DOI:10.1021/acsami.9b20041

[2]	Phase-Engineered Molybdenum Telluride/Black Phosphorus Van der Waals Heterojunctions for Tunable Multivalued Logic ACS Applied Materials & Interfaces, 2020 DOI:10.1021/acsami.9b20041

[3]	Gate Quantum Capacitance Effects in Nanoscale Transistors Nano Letters, 2019 DOI:10.1021/acs.nanolett.9b02660

[4]	Gate Quantum Capacitance Effects in Nanoscale Transistors Nano Letters, 2019 DOI:10.1021/acs.nanolett.9b02660

[5]	Multivalued logic implementation using Quantum dot gate non-volatile memory 2019 IEEE Long Island Systems, Applications and Technology Conference (LISAT), 2019 DOI:10.1109/LISAT.2019.8817344

[6]	Dual Quantum Dot Superlattice International Journal of High Speed Electronics and Systems, 2018 DOI:10.1142/S0129156418400037