Dynamic and Leakage Power Estimation in Register Files Using Neural Networks

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.org/journal/cs
E-mail: cs@scirp.org

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"Dynamic and Leakage Power Estimation in Register Files Using Neural Networks"
written by Assim A. Sagahyroon, Jamal A. Abdalla,
published by Circuits and Systems, Vol.3 No.2, 2012

has been cited by the following article(s):

[1]	Power Prediction in Register Files Using Machine Learning
	IEEE Access, 2022

[2]	RTL to Transistor Level Power Modelling and Estimation Techniques for FPGA and ASIC: A Survey
	2020

[3]	An Efficient Computer-Aided Design Methodology for FPGA&ASIC High-Level Power Estimation Based on Machine Learning
	2019

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[1]	Power Prediction in Register Files Using Machine Learning IEEE Access, 2022 DOI:10.1109/ACCESS.2022.3172287

[2]	RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021 DOI:10.1109/TCAD.2020.3003276