High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)

ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.org/journal/cs
E-mail: cs@scirp.org

Citations h5-index & Ranking*

"High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)"
written by Raed Bani-Hani, Salah Harb, Khaldoon Mhaidat, Eyad Taqieddin,
published by Circuits and Systems, Vol.5 No.3, 2014

has been cited by the following article(s):

[1]	High-performance AES-128 algorithm implementation by FPGA-based SoC for 5G communications.
	2021

[2]	HIGH-DENSITY INFORMATION SECURE STORAGE METHOD FOR BIG DATA CENTER BASED ON FUZZY CLUSTERING.
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[3]	HIGH-DENSITY INFORMATION SECURE STORAGE METHOD FOR BIG DATA CENTER BASED ON FUZZY CLUSTERING
	Academic Journal of Manufacturing Engineering, 2020

[4]	A Novel Hardware-Efficient Central Pattern Generator Model Based on Asynchronous Cellular Automaton Dynamics for Controlling Hexapod Robot
	2020

[5]	10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 …
	2020

[6]	Design and implementation of encrypted file system based on FPGA
	2019

[7]	A dynamic reconfigurable design of multiple cryptographic algorithms based on FPGA
	2018

[8]	Scalable and Low Overhead Watermarking Based Integrated Authentication and Encryption Scheme for Wireless Sensor Networks
	2017

[9]	First steps towards designing a compact language for the description of logic circuits
	2016

[10]	Pipelining Concept for Low Power DES Implementation
	International Journal of Computer Applications Technology and Research, 2016

[11]	Image and data processing using reconfigurable computer systems
	Advances in Computer Science, 2015

[12]	MASTER OF TECHNOLOGY

[1]	High Throughput PRESENT Cipher Hardware Architecture for the Medical IoT Applications Cryptography, 2023 DOI:10.3390/cryptography7010006

[2]	A Novel Hardware-Efficient Central Pattern Generator Model Based on Asynchronous Cellular Automaton Dynamics for Controlling Hexapod Robot IEEE Access, 2020 DOI:10.1109/ACCESS.2020.3012706

[3]	10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform Electronics, 2020 DOI:10.3390/electronics9101665

[4]	A Dynamic Reconfigurable Design of Multiple Cryptographic Algorithms Based on FPGA 2018 IEEE International Conference on Smart Internet of Things (SmartIoT), 2018 DOI:10.1109/SmartIoT.2018.00-17

[5]	First steps towards designing a compact language for the description of logic circuits 2016 International Conference on Communications (COMM), 2016 DOI:10.1109/ICComm.2016.7528313