"Characterization of a Novel Low-Power SRAM Bit-Cell Structure at Deep Sub-Micron CMOS Technology for Multimedia Applications"
written by Rakesh Kumar Singh, Manisha Pattanaik, Neeraj Kr. Shukla,
published by Circuits and Systems, Vol.3 No.1, 2012
has been cited by the following article(s):
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[6] A Roadmap on the Low Power Static Random Access Memory Design Topologies
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[10] Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology using N-Curve
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[11] Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications
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[12] Analysis of Subthreshold Leakage Current in IP 3 SRAM Bit-Cell under Temperature Variations in Deep-Submicrometer CMOS Technology
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[13] Analysis of Gate Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in DSM Technology
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[14] Implementation of high performance and low leakage half subtractor circuit using AVL technique
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[15] An Analysis of Power and Stability in 6T, NC, Asymmetric, PP, and P3SRAM Bit-Cells Topologies in 45nm CMOS Technology
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[16] Analysis and Simulation of Subthreshold Leakage Current Reduction in IP3 SRAM Bit-Cell at 45 nm CMOS Technology for Multimedia Applications
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