Author(s)

Antonios N. Dadaliaris¹, Panagiotis Oikonomou², Maria G. Koziri¹, Evangelia Nerantzaki¹, Thanasis Loukopoulos³, Georgios I. Stamoulis²

¹Department of Computer Science, University of Thessaly, Lamia, Greece.
²Department of Electrical and Computer Engineering, University of Thessaly, Volos, Greece.
³Department of Computer Science and Biomedical Informatics, University of Thessaly, Lamia, Greece.

Standard cell placement algorithms have been at the forefront of academic research concerning the physical design stages of VLSI design flows. The penultimate step of a standard cell placement procedure is legalization. In this step the manufacturability of the design is directly settled, and the quality of the solution, in terms of wirelength, congestion, timing and power consumption is indirectly defined. Since the heavy lifting regarding processing is performed by global placers, fast legalization solutions are protruded in state-of-the-art design flows. In this paper we propose and evaluate a legalization scheme that surpasses in execution speed two of the most widely used legalizers, without not only corrupting the quality of the final solution in terms of interconnection wirelength but improving it in the process.

Legalization, Standard Cell Placement, Heuristics, Interconnect Wirelength

Dadaliaris, A. , Oikonomou, P. , Koziri, M. , Nerantzaki, E. , Loukopoulos, T. and Stamoulis, G. (2017) A Connectivity-Based Legalization Scheme for Standard Cell Placement. Circuits and Systems, 8, 191-201. doi: 10.4236/cs.2017.88013.