Author(s)

Hung-Yu Chen¹, Yuan-Kai Wang²

¹Graduate Institute of Applied Science and Engineering, Fu Jen Catholic University, New Taipei city.
²Department of Electrical Engineering, Fu Jen Catholic University, New Taipei city.

Moving object detection including background subtraction and morphological processing is a critical research topic for video surveillance because of its high computational loading and power consumption. This paper proposes a hardware design to accelerate the computation of background subtraction with low power consumption. A real-time background subtraction method is designed with a frame-buffer scheme and function partition to improve throughput, and implemented using Verilog HDL on FPGA. The design parallelizes the computations of background update and subtraction with a seven-stage pipeline. A stripe-based morphological processing and accounting for the completion of detected objects is devised. Simulation results for videos of VGA resolutions on a low-end FPGA device show 368 fps throughput for only the real-time background subtraction module, and 51 fps for the whole system, including off-chip memory access. Real-time efficiency with low power consumption and low resource utilization is thus demonstrated.

Background Substraction, Moving Object Detection, Field Programmable Gate Array (FPGA), Hardware Acceleration

Chen, H. and Wang, Y. (2016) Hardware Design of Moving Object Detection on Reconfigurable System. Journal of Computer and Communications, 4, 30-43. doi: 10.4236/jcc.2016.410004.