Author(s)

Kodai Ueyoshi¹, Takao Marukame², Tetsuya Asai¹, Masato Motomura¹, Alexandre Schmid²

¹Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan.
²Swiss Federal Institute of Technology, Lausanne, Switzerland.

Restricted Boltzmann Machines (RBMs) are an effective model for machine learning; however, they require a significant amount of processing time. In this study, we propose a highly parallel, highly flexible architecture that combines small and completely parallel RBMs. This proposal addresses problems associated with calculation speed and exponential increases in circuit scale. We show that this architecture can optionally respond to the trade-offs between these two problems. Furthermore, our FPGA implementation performs at a 134 times processing speed up factor with respect to a conventional CPU.

Deep Learning, Restricted Boltzmann Machines (RBMs), FPGA, Acceleration

Ueyoshi, K. , Marukame, T. , Asai, T. , Motomura, M. and Schmid, A. (2016) FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines. Circuits and Systems, 7, 2132-2141. doi: 10.4236/cs.2016.79185.