Author(s)

Erulappan Sakthivel¹, Kasinathan Pounraj¹, Veluchamy Malathi², Muruganantham Arunraja¹, Govindaraj Perumalvignnesh³

¹Electrical and Electronics Engineering, SBM College of Engineering, Dindigul, India.
²Electrical and Electronics Engineering, Anna University Regional Campus, Madurai, India.
³Electrical and Electronics Engineering, The Silicon Harvest, Madurai, India.

This paper describes the design and Field Programmable Gate Array (FPGA) based 4 × 4 breadth heuristic Multiple-Input—Multiple-Output (MIMO) decoder using 16 and 64 Quadrature Amplitude Modulation (QAM) schemes. The intention of this work is to observe the performance of Candidate Execution with Low Latency Approach for soft MIMO detector in FPGA (CELLA). The Smart Ordering and Candidate Adding (SOCA), Parallel Candidate Adding (PCA) and Backward Candidate Adding (BCA) give better performance in terms of Bit Error Rate (BER) or chip level service. In order to attain both BER and FPGA level performance in a single system, CELLA is developed in this work. Simulation and experimental results demonstrate the effectiveness of the proposed work under the system 4 × 4 MIMO-OFDM employing 16 QAM and 64 QAM. The proposed experiment is implemented in Xilinx Virtex 5 C5VSX240T. The performance results, in terms of FPGA level 76% slice reduction, 58.76% throughput improvement, 75% power reduction and 87% latency reduction, are achieved. The BER performance is observed and compared with the conventional algorithms. Thus, the proposed work achieves better outcome than the conventional work.

Multiple-Input—Multiple-Output (MIMO), Field Programmable Gate Array, Parallel Candidate Adding

Sakthivel, E. , Pounraj, K. , Malathi, V. , Arunraja, M. and Perumalvignnesh, G. (2016) CELLA: FPGA Based Candidate Execution with Low Latency Approach for Soft MIMO Detector. Circuits and Systems, 7, 1760-1768. doi: 10.4236/cs.2016.78152.