Author(s)

Sivaranjani Paramasivam¹, Senthilkumar Athappan², Eswari Devi Natrajan¹, Maheswaran Shanmugam¹

¹Department of Electronics and Communication Engineering, Kongu Engineering College, Erode, India.
²Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, India.

Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.

VLSI Non-Slicing Floorplan, Modified Corner List (MCL) Algorithm, Hybrid Particle Swarm Optimization-Harmony Search Algorithm (HPSOHS)

Paramasivam, S. , Athappan, S. , Natrajan, E. and Shanmugam, M. (2016) Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm. Circuits and Systems, 7, 562-573. doi: 10.4236/cs.2016.75048.