Author(s)

Qassim Nasir, Saleh Al-Araji

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Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) is used to linearize the phase difference detection, and enhance the loop performance. The loop has faster acquisition, less steady state phase error, and wider locking range compared to the conventional ZCDPLL. This work presents a Zero Crossing Digital Phase Locked Loop with Arc Sine block (ZCDPLL-AS). The performance of the loop is analyzed under mobile faded channel conditions. The mobile channel is assumed to be two path fading channel corrupted by additive white Gaussian noise (AWGM). It is shown that for a constant filter gain, the frequency spread has no effect on the steady state phase error variance when the loop is subjected to a phase step. For a frequency step and under the same conditions, the effect on phase error is minimal.

Non-Uniform Sampling, Digital Phase Locked Loops, Zero Crossing DPLL, Mobile Faded Channels

Q. Nasir and S. Al-Araji, "Linearized Phase Detector Zero Crossing DPLL Performance Evaluation in Faded Mobile Channels," Circuits and Systems, Vol. 2 No. 3, 2011, pp. 139-144. doi: 10.4236/cs.2011.23021.