Author(s)

Hiroshi Makino, Naoya Okada, Tetsuya Matsumura, Koji Nii, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda

Design Platform Development Division, Renesas Electronics Corporation, Kodaira, Japan.
Faculty of Engineering, Osaka Institute of Technology, Osaka, Japan.
Faculty of Information Science and Technology, Osaka Institute of Technology, Hirakata, Japan.
Graduate School of Natural Science, Kanazawa University, Kanazawa, Japan.
SoC Software Platform Division, Renesas Electronics Corporation, Itami, Japan.

An accelerated evaluation method for the SRAM cell write margin is proposed using the conventional Write Noise Margin (WNM) definition based on the “butterfly curve”. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is chosen in order to make the access transistor operate in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The WNM shift amount is determined from the measured WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. Together with the maximum likelihood method, a normal distribution of the AWNM drastically improves development efficiency because the write failure probability can be estimated from a small number of samples. The effectiveness of the proposed method is verified using the Monte Carlo simulation.

Static Random Access Memory (SRAM); Write Noise Margin (WNM); Vth Fluctuation; Variance; WNM Distribution

H. Makino, N. Okada, T. Matsumura, K. Nii, T. Yoshimura, S. Iwade and Y. Matsuda, "Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration," Circuits and Systems, Vol. 3 No. 3, 2012, pp. 242-251. doi: 10.4236/cs.2012.33034.