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Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique
(Articles)
S. K. Manikandan
,
C. Palanisamy
Circuits and Systems
Vol.7 No.9
,July 27, 2016
DOI:
10.4236/cs.2016.79224
2,205
Downloads
4,959
Views
Citations
Implementation of
N
-Bit Binary Multiplication Using
N
- 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method
(Articles)
M. Nisha Angeline
,
S. Valarmathy
Circuits and Systems
Vol.7 No.9
,July 19, 2016
DOI:
10.4236/cs.2016.79203
1,769
Downloads
3,030
Views
Citations
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