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Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study
National Academy Science Letters,
2019
DOI:10.1007/s40009-019-00830-0
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[2]
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Impact of TSV location in HVIC on CMOS operation: A mixed-mode TCAD simulation study
Microelectronics Journal,
2018
DOI:10.1016/j.mejo.2018.03.008
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[3]
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An efficient and simple compact modeling approach for 3-D interconnects with IC׳s stack global electrical context consideration
Microelectronics Journal,
2015
DOI:10.1016/j.mejo.2014.12.002
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