TITLE:
Area Efficient Sparse Modulo 2n - 3 Adder
AUTHORS:
Ritesh Kumar Jaiswal, Chatla Naveen Kumar, Ram Awadh Mishra
KEYWORDS:
Residue Number System (RNS), Parallel Prefix Adder, End Around Carry (EAC), Sparse Adder
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.12,
October
31,
2016
ABSTRACT: This paper presents area efficient
architecture of modulo 2n - 3 adder. Modulo adder is one of the main components
for the implementation of residue number system (RNS) based applications. The
proposed modulo 2n - 3 adder is implemented effectively, which utilizes
parallel prefix and sparse concepts. The carries of some bits are calculated
with the help of sparse approach in log2n prefix levels. This scheme is
implemented with the help of idempotency property of the parallel prefix carry
operator and its consistency. Parallel prefix structure contributes to fast
carry computation. This will reduce area as well as routing complexity
efficiently. The presented adder has double representation of residues in {0,
1, and 2}. The proposed adder offers significant reduction in area as the
number of bits increases.