S. Y. Lee and J. Y. Hsieh, “Analysis and Implementation of a 0.9 V Voltage-Controlled Oscillator with Low Phase Noise and Low Power Dissipation,” IEEE Transactions on Circuits and Systems II, Vol. 55, No. 7, July 2008, pp. 624-627. doi:10.1109/TCSII.2008.921574

has been cited by the following article:

• TITLE: Voltage Controlled Ring Oscillator Design with Novel 3 Transistors XNOR/XOR Gates

  AUTHORS: Manoj Kumar, Sandeep Kumar Arya, Sujata Pandey

  KEYWORDS: CMOS, Delay Cell, Low Power, VCO, XOR and XNOR Gates

  JOURNAL NAME: Circuits and Systems, Vol.2 No.3, July 11, 2011

  ABSTRACT: In present work, improved designs for voltage controlled ring oscillators (VCO) using three transistors XNOR/XOR gates have been presented. Supply voltage has been varied from [1.8 - 1.2] V in proposed designs. In first method, the VCO design using three XNOR delay cells shows frequency variation of [1.900 - 0.964] GHz with [279.429 - 16.515] µW power consumption variation. VCO designed with five XNOR delay cells shows frequency variation of [1.152 - 0.575] GHz with varying power consumption of [465.715 - 27.526] µW. In the second method VCO having three XOR stages shows frequency variation [1.9176 - 1.029] GHz with power consumption variation from [296.393 - 19.051] µW. A five stage XOR based VCO design shows frequency variation [1.049 - 0.565] GHz with power consumption variation from [493.989 - 31.753] µW. Simulations have been performed by using SPICE based on TSMC 0.18µm CMOS technology. Power consumption and output frequency range of proposed VCOs have been compared with earlier reported circuits and proposed circuit’s shows improved performance.