TITLE:
Predictive Prefetching for Parallel Hybrid Storage Systems
AUTHORS:
Maen M. Al Assaf
KEYWORDS:
Predictive Prefetching, Probability Graph, Parallel Storage Systems, Hybrid Storage System
JOURNAL NAME:
International Journal of Communications, Network and System Sciences,
Vol.8 No.5,
May
14,
2015
ABSTRACT: In this
paper, we present a predictive prefetching mechanism that is based on
probability graph approach to perform prefetching between different levels in a
parallel hybrid storage system. The fundamental concept of our approach is to
invoke parallel hybrid storage system’s parallelism and prefetch data among
multiple storage levels (e.g. solid state disks, and hard disk drives) in
parallel with the application’s on-demand I/O reading requests. In this study,
we show that a predictive prefetching across multiple storage levels is an
efficient technique for placing near future needed data blocks in the uppermost
levels near the application. Our PPHSS approach extends previous ideas of
predictive prefetching in two ways: (1) our approach reduces applications’
execution elapsed time by keeping data blocks that are predicted to be accessed
in the near future cached in the uppermost level; (2) we propose a parallel
data fetching scheme in which multiple fetching mechanisms (i.e. predictive prefetching and
application’s on-demand data requests) can work in parallel; where the first
one fetches data blocks among the different levels of the hybrid storage
systems (i.e. low-level (slow) to
high-level (fast) storage devices) and the other one fetches the data from the
storage system to the application. Our PPHSS strategy integrated with the
predictive prefetching mechanism significantly reduces overall I/O access time
in a hybrid storage system. Finally, we developed a simulator to evaluate the
performance of the proposed predictive prefetching scheme in the context of
hybrid storage systems. Our results show that our PPHSS can improve system
performance by 4% across real-world I/O traces without the need of using large
size caches.