D. Stepanović and B. Nikolió, “A 2.8 GSPs 44.6 mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 4, 2013.

has been cited by the following article:

• TITLE: A Timing Skew Calibration Scheme in Time-Interleaved ADC

  AUTHORS: Jing Li, Yang Liu, Hao Liu, Shuangyi Wu, Ning Ning, Qi Yu

  KEYWORDS: Timing Skew; Background Calibration; Time-Interleaved; Analog-to-Digital Converters

  JOURNAL NAME: Journal of Computer and Communications, Vol.1 No.6, November 26, 2013

  ABSTRACT: This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.