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2010 Asia-Pacific Conference on Information Theory (APCIT 2010 E-BOOK)

Xi'an,China,10.1-10.2,2010

ISBN: 978-1-935068-47-1 Scientific Research Publishing, USA

E-Book 506pp Pub. Date: November 2010

Category: Computer Science & Communications

Price: $80

Title: A Faster and Effective Hardware Simulation Design Based on Decoder
Source: 2010 Asia-Pacific Conference on Information Theory (APCIT 2010 E-BOOK) (pp 203-206)
Author(s): Li Guo, Xi’an Communication Institute, Xi’an 710106, China
Zhuoqin Jiang, Xi’an Communication Institute, Xi’an 710106, China
Abstract: In this paper, a highly optimized hardware simulation design to operate 2-D product code it- erative decoder is presented. This decoder hardware test bench is faster than traditional soft simulation methods to achieve the same level of BER lower than 10-9 .The BER results that were obtained with the hardware simulation in less than 4 hours would require over 40 hours to complete soft simulation ,so it is shown that the hardware simulation design will improve simulation efficiency greatly. The summary of bit errors on different signal to noise ratio(SNR) of input signals is given ,In addition to, simulation waves is also given to report number of decoded bit errors for SNR=9dB condition. Using this approach the result of Bit Errors can be obtained from simulation waves. Obviously, this design not only simulates quickly, but also data analyzes conveniently. With changing encoder module and decoder module flexi- bly, this hardware test bench is developed to test the BER performance of the various channel decod- ers .So this hardware test bench is proved validity and feasibility.
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