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2010 National Conference of Higher Vocational and Technical Education on Computer Information (NCHVT 2010 E-BOOK)

Rizhao,China,12.4-12.5，2010

ISBN: 978-1-935068-31-0 Scientific Research Publishing, USA

E-Book 358pp Pub. Date: December 2010

Category: Social Sciences & Humanities

Price: $70

Title: AES Encryption and Decryption Algorithm for High-Speed Design FPGA-Based
Source: 2010 National Conference of Higher Vocational and Technical Education on Computer Information (NCHVT 2010 E-BOOK) (pp 266-270)
Author(s): Yong-hong Zhou, Physics and Electronic Information College, China West Normal University，Nan Chong 637002, China
Jin-xiang Shao, Da Qing Oilfield Co., Ltd. 7th Oil Production Plant，Da Qing 16357, China
Shun-wen Xiao, Physics and Electronic Information College, China West Normal University，Nan Chong 637002, China
Zheng-ming Tang, Physics and Electronic Information College, China West Normal University，Nan Chong 637002, China
Abstract: For the widely used 32-bit data platform, implementation of AES-128 encryption / decryption algorithm designing on FPGA. Encryption/decryption unit uses part of the external pipeline technology, using logical lock technology optimized S-BOX and key storage in the system optimization. With less system resources, in the 100MHz clock frequency, obtained 3200Mbit/s data throughput. Applies to clock frequency is not higher than 100MHz the mid-and low-end equipment.
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