The 15th Conference on the Wireless across the Taiwan straits (WRTS 2010 E-BOOK)

Kunming,China,9.12-9.17,2010

ISBN: 978-1-935068-21-1 Scientific Research Publishing, USA

E-Book 350pp Pub. Date: September 2010

Category: Computer Science & Communications

Price: $80

Title: A 8-Bit Pipelined ADC Using Sub-Sampling and Sharing Techniques
Source: The 15th Conference on the Wireless across the Taiwan straits (WRTS 2010 E-BOOK) (pp 257-261)
Author(s): Mingchieh Tsai, Electrical Engineering Tatung University, Zhongshan, 104, Taiwan
Shangwen Yu, Electrical Engineering Tatung University, Zhongshan, 104, Taiwan
Abstract: An analog to digital interface is required between the received analog signal and DSP system and portable consumer electronics. The demand for low-power integrated circuits is indispensable. Among ADC architectures, pipelined ADCs are the most suitable for medium/high speed and resolution applications. In this thesis, a 8-bit 50-MHz pipelined analog-to-digital converter consisting of 1.5-bit/stage has been designed in TSMC 0.18μm 1P6M CMOS process. In order to decrease noise interference, the whole circuit is designed by fully differential structure. And for achieving a low power and small area pipelined ADC, this thesis merges op-amp sharing, sub-sampling and sub-ADC sharing. The pipeline ADC is simulated by HSPICE. For 1.123046875MHz sine wave input, the SNDR is 47.66 dB, the differential input range is ± 1V, and the power consumption is 62.44mW.
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