A Review of PVT Compensation Circuits for Advanced CMOS Technologies

Andrey Malkov, Dmitry Vasiounin, Oleg Semenov

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DOI: 10.4236/cs.2011.23024                

Abstract

The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and output load variations. As the interface speed grows up, the output drivers have been important component for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the output drivers. The output driver impedance compliance with the transmission line is a key factor in noise minimization due to the signal reflections. In this paper, the different implementations of PVT compensation circuits are analyzed for cmos45nm and cmos65nm technology processes. One of the considered PVT compensation circuits uses the analog compensation approach. This circuit was designed in cmos45nm technology. Other two PVT compensation circuits use the digital compensation method. These circuits were designed in cmos65nm technology. Their electrical characteristics are matched with the requirements for I/O drivers with respect to DDR2 and DDR3 standards. DDR2 I/O design was done by the Freescale wireless design team for mobile phones and later was re-used for other high speed interface designs. In conclusion, the advantages and disadvantages of considered PVT control circuits are analyzed.

Keywords

PVT Compensation, PVT Control Circuit, Process Variation, DDR Interface, I/O Driver

Conflicts of Interest

The authors declare no conflicts of interest.

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