Computation of Error in Estimation of Nonlinearity in ADC Using Histogram Technique

Radhe Shyam Gamad, Deepak Kumar Mishra

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DOI: 10.4236/eng.2011.36069                

Abstract

Computation of error in estimation of nonlinearity in ADC using histogram test are reported in this paper. Error determination in estimation of Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) of an ADC is done by taking deviation of estimated value from actual value. Error in estimated INL and DNL is determined to check the usefulness of basic histogram test algorithm. Arbitrary error is introduced in ideal simulated ADC transfer characteristics and full scale simulated sine wave is applied to ADC for computation of error in estimation of transition levels and nonlinearity. Simulation results for 5 and 8 bit ADC are pre-sented which show effectiveness of the proposed method.

Keywords

Nonlinearity, Transfer Characteristics, Code Bin Width, Error Estimation, Transition Levels

Conflicts of Interest

The authors declare no conflicts of interest.

References

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