Conduction Mechanism Analysis of Inversion Current in MOS Tunnel Diodes

Ayşe Evrim Saatci, Orhan Özdemir, Kubilay Kutlu

Department of Physics, Yildiz Technical University, Istanbul, Turkey.

DOI: 10.4236/msa.2013.412101                

Abstract

Self inversion issue and excess capacitance phenomenon were observed for the first time in relatively thick silicon dioxide (SiO₂) in the form of MOS (metal(Al)/SiO₂/p type crystalline silicon) structure. Both phenomena were based on minority carriers (electrons in this case) and studied through DC current-applied bias voltage (I-V) and AC admittance measurements in dark/light condition as a function of ambient temperature (295 - 380 K). Either of the cases was the departure of traditional MOS analysis, manifesting themselves in the inversion regime of MOS diode. Increase in frequency/temperature/light intensity within dark and light conditions led to weaken the maxima of hump in C-V curves and finally turned into deep depletion mode after exceeding threshold value of frequency/temperature/light intensity. In resumed conditions, supplementary I-V measurements were carried out to describe the generation and conduction mechanism(s) for minority carriers (electrons).

Keywords

Excess Capacitance; MOS; Selfly Inverted Region; Tunneling Based Inversion Currents

1. Introduction

Electrical properties of Metal-Oxide-Semiconductor (MOS) tunnel diodes, MOSTD, have been attractive due to technological and fundamental physical viewpoints. Though the scaling down of c-MOS integrated circuits leads to significant tunneling current and is a major concern, it also provides an opportunity to study transport phenomena in order to be utilized in light emitting diodes (LED) [1,2] photodetectors [3] and solar cells [4-6].

Inversion region is composed of minority carriers and measured inversion current of MOS diodes could be originated through band to bulk trap and/or band to band tunnelling, and interface state tunnelling [7,8]. Self inversion in MOS structure beyond the gate electrode is a last minority carrier generation model [9-13]. Usually, tunnelling rate and/or generation rate of minority carriers determine the amount of current flowing in MOSTD’s where the semiconductor surface is inverted near zero bias [14,15]. As the applied reverse bias increases, inversion regime becomes strong and hence tunneling current increases abruptly. In the forward direction, the semiconductor goes first from inversion to depletion and then depletion to accumulation regimes as applied bias is scanned from negative to positive bias side. The transition of defined regimes for MOS structure appears as a hump in current-bias voltage (I-V) curves and marks the semiconductor limited to tunnel limited behavior. This kind of hump in I-V curves is also observed in hydrogenated amorphous silicon (a-Si:H)/c-Si [16], micro c-Si/ c-Si [17], and silicon quantum dots embedded in SiO₂ insulator film/Si [18,19] structure.

Recently, Lin et al. [20] discussed the generation rate of electron-hole (e-h) pairs in Aluminum(Al)-SiO₂- p/p⁺/p⁺⁺-c-Si MOSTD’s where p⁺/p⁺⁺ represents high doping concentrations of c-Si (above 10¹⁸ cm⁻³). Their observations show that the generation rate of e-h pairs is mainly limited via band to traps tunneling and band to band tunneling rather than conventional Schockley-ReadHall (SRH) statistic model [21,22]. Noteworthy, the transition of band to bulk trap tunneling in depletion layer of c-Si into band to band tunneling through interface traps also exhibits a hump in both computed and experimentally determined I-V curves. Furthermore, band to traps and band to band tunneling models are identified by determining the value of activation energy (E_A) as well as their dependences on temperature/light illumination.

Correponding to the hump in I-V curves, theoretical as well as experimental analysis of MOSTD’s indicates similar hump behavior in capacitance-voltage (C-V) curves [7,8,14,15] in minority carrier devices. The onsets and breaking off of hump in capacitance correspond to the transition from semiconductor-limited to tunnel-limited behavior as in I-V curves. Moreover, it is explored that hump has both frequency and work function dependent on chosen metal as electrodes since metals having a low work function like magnesium (Mg) invert the insulator/semiconductor interface at zero bias [7,8,14, 15].

This work discusses the self inversion issue and excess capacitance phenomenon observed for the first time in relatively thick insulator film within MOS structure. In self inversion, minority carriers pile up at SiO₂/p-c-Si interface without applying external bias voltage. Those pre-existent electrons could be originated from either ion migration along the surface of insulator during application of prolonged bias voltage or proton diffusion adjacent to insulator/semiconductor interface within a moisture ambient. Due to the electrons, surface bands are bent, creating inversion regime without external bias voltage. Drastic influence takes place especially in this regime of MOS structure such that quasi-static C-V curve is observed for a huge ac modulation frequency (above 100 kHz). This kind of C-V behavior manifests itself as conductivity modulation in I-V measurement and getting such behavior is owing to the injection of minority carrier into the depletion region of junction. Consequently, an extra hole should be supplied to conserve the neutrality conditions, leading to change of the resistivity of diode. Such findings appear as conductivity modulation in I-V measurement and excess capacitance in C-V measurement. Within this context, integrated self inversion issue and excess capacitance phenomenon are considered to interprete anormal C-V feature in inversion regime of MOS structure at hand.

2. Film Fabrication and Experimental Tools

Boron doped and (100) oriented silicon (p-Si) wafer, grown by Czochralski method with 1 - 3 W cm resistivity and 400 µm thicknesses was cleaned chemically via RCA cleaning procedure prior to oxidation. SiO₂ insulator film was grown thermally at 1000˚C with dry oxygen (O₂) which flew with a constant rate of 600 sccm for 120 min. Backside was coated with Al when the system was pumped down to 10⁻⁶ Torr. Then, wafer was annealed to have ohmic contact at 590˚C under N₂ ambient for 15 min. Finally, gate (front) electrode of the diodes was formed directly by evaporating Al through copper masks of diameter around 0.1 cm to obtain MOS structure.

For electrical analysis, I-V measurement was performed as a function of temperature in the range between 295 K and 380 K in dark/light condition by Keithley 6517A multimeter. Light illumination was carried out by tungsten lamp. In resumed conditions, capacitance (C) and conductance/frequency (G/ω) as a function of dc gate bias voltage (V_G) and its ac voltage modulation frequency (ω) were performed by HP4192A Impedance Analyzer (400 Hz to 1 MHz). Computer controlled LABWIEW program was facilitated to conduct measurements.

3. Results and Discussion

3.1. Dark/Light Current-Voltage Measurement at Room Temperature

Figure 1(a) depicts the I-V variation of Al/SiO₂/p-cSi/Ohmic Al MOS tunnel diode in dark and different intensity of light exposure at room temperature. The characteristic with Al as gate electrode demonstrates a consistent minority carrier behavior under small forward and reverse biases [7,8,14,15]. As clear from Figure 1(a), three distinctly different conduction mechanisms are eventual under positively applied gate bias region: under low bias region where V is less than 1 V, sharp increase in current with applied voltage is observed. For the intermediate bias voltage region, 1 < V < 2.5 V, rate in increase reduces and becomes sharp again when V exceeds 3.5 V, exhibiting the onset of last conductive region. These regions illustrate the variation of transport mechanisms in dark I-V curve. Under weak (15 mW/cm²) and strong light illumination (100 mW/cm²), current in negative applied bias shows no drastic change. For the positive side, on the other hand, transition of one to another mechanism becomes smoother and subsequently light insensitive regions comes up around 7.5 V under dark/illuminated condition.In brief, temperature dependent I-V characteristics are required to determine governing generation/conduction mechanisms.

Conflicts of Interest

The authors declare no conflicts of interest.

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