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Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

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DOI: 10.4236/cs.2013.43037    4,051 Downloads   5,667 Views   Citations

ABSTRACT

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

Ahmed, O. , Abu-Elyazeed, M. , Abdelhalim, M. , Amer, H. and Madian, A. (2013) Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits. Circuits and Systems, 4, 276-279. doi: 10.4236/cs.2013.43037.

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