Performance Prospects of Fully-Depleted SOI MOSFET-Based Diodes Applied to Schenkel Circuit for RF-ID Chips

Yasuhisa Omura, Yukio Iida

Department of Electric, Electronics and Informatics, Kansai University, Suita, Japan.

DOI: 10.4236/cs.2013.42024                

Abstract

The feasibility of using the SOI-MOSFET as a quasi-diode to replace the Schottky-barrier diode in the Schenkel circuit is examined by device simulations primarily and experiments partly. Practical expressions of boost-up efficiency for d. c. condition and a. c. condition are proposed and are examined by simulations. It is shown that the SOI-MOSFET-based quasi-diode is a promising device for the Schenkel circuit because high boost-up efficiency can be gained easily. An a. c. analysis indicates that the fully-depleted condition should hold to suppress the floating-body effect for GHz-level RF applications of a quasi-diode.

Keywords

RF-ID; Schenkel Circuit; SOI-MOSFET; Quasi-Diode; Low-Power

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	U. Karthaus and M. Fischer, “Fully Integrated Passive UHF RFID Transponder IC with 16.7-μW Minimum RF Input Power,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 10, 2003, pp.1602-1608.
[2]	M. Usami and M. Ohki, “The μ-Chip: Ultra-Small 2.45 GHz RFID Chip for Ubiquitous Recognition Applications,” IEICE Transactions on Electronics, Vol. E86-C, No. 4, 2003, pp.521-528.
[3]	W. Jeon, T. M. Firestone, J. C. Rodgers and J. Melngailis, “Design and Fabrication of Schottky Diode, On-Chip RF Power Detector,” Solid-State Electronics, Vol. 48, No. 10-11, 2004, pp. 2089-2093.
[4]	B. Strassner and K. Chang, “Passive 5.8-GHz Radio-Frequency Identification Tag for Monitoring Oil Drill Pipe,” IEEE Transactions on Microwave Theory and Techniques, Vol. 51, No. 2, 2003, pp. 356-363. doi:10.1109/TMTT.2002.807832
[5]	K. Ahsan, H. Shah and P. Kingston, “RFID Applications: An Introductory and Exploratory Study,” International Journal of Computer Science Issues, Vol. 7, No. 1, 2010, pp. 1-7.
[6]	Y. Kado, M. Suzuki, K. Koike, Y. Omura and K. Izumi, “A 1 GHz/0.9 mW CMOS/SIMOX Divide-by-128/129 Dual-Modulus Prescaler Using a Divide-by-2/3 Synchro nous Counter,” IEEE Journal of Solid-State Circuits, Vol. 28, No. 4, 1993, pp. 513-517.
[7]	O. Rozeau, J. Jomaah, J. Boussey and Y. Omura, “Comparison between High and Low-Dose Separation by Implanted Oxygen MOS Transistors for Low-Power Radio Frequency Applications,” Japanese Journal of Applied Physics, Vol. 39, No. 4B, 2000, pp. 2264-2267. doi:10.1143/JJAP.39.2264
[8]	J. P. Raskin, A. Viviani, D. Flandre and J.-P. Colinge, “Substrate Crosstalk Reduction Using SOI Technology,” IEEE Transactions on Electron Devices, Vol. 44, No. 12, 1997, pp. 2252-2261. doi:10.1109/16.644646
[9]	Y. Omura, “Negative Conductance Properties in Extremely Thin Silicon-on-Insulator Insulated-Gatepn-Junction De vices (Silicon-on-Insulator Surface Tunnel Transistor),” Japanese Journal of Applied Physics, Vol. 35, No. 11A, 1996, pp. L1401-L1403. doi:10.1143/JJAP.35.L1401
[10]	Y. Omura and T. Tochio, “Significant Aspects of Minor ity Carrier Injection in Dynamic-Threshold SOI MOS FET at Low Temperature,” Cryogenics, Vol. 49, No. 11, 2009, pp. 611-614. doi:10.1016/j.cryogenics.2008.11.009
[11]	Synopsys Inc., “TCAD-DESSIS/GENESISe Operation Man ual,” ver. 7.5. http://www.sysnopsys.com/
[12]	Microsim Corp., “PSpice Reference Manual.” http://www.microsimcom.com/
[13]	K. Takahashi, S. Y. Wang and M. Mizunuma, “Comple mentary Charge Pump Booster,” Electronics and Communications in Japan Part II-Electronics, Vol. 82, No. 6, 1999, pp. 73-81. doi:10.1002/(SICI)1520-6432(199906)82:6<73::AID-ECJB8>3.0.CO;2-C
[14]	Y. Taur and T. H. Ning, “Fundamentals of Modern VLSI Devices,” Cambridge University Press, Cambridge, 1998.
[15]	Y. Kado, M. Suzuki, K. Koike, Y. Omura and K. Izumi, “An Experimental Full-CMOS Multi-gigahertz PLL LSI Using 0.4-μm Gate Ultrathin-Film SIMOX Technology,” IEICE Transactions on Electronics, Vol. E76-C, No. 4, 1993, pp. 562-571.
[16]	C. Wann, F. Assaderaghi, L. Shi, K. Chan, S. Cohen, H. Hovel, K. Jenkins, Y. Lee, D. Sadana, R. Viswanathan, S. Wind and Y. Taur, “High-Performance 0.07-μm CMOS with 9.3-ps Gate Delay and 150 GHz fT,” IEEE Electron Devices Letters, Vol. 18, No. 12, 1997, pp. 625-627. doi:10.1109/55.644091
[17]	J.-P. Colinge, “Silicon-on-Insulator: Materials to VLSI,” 3rd Edition, Kluwer Academic Publishing, Dordrecht, 2004. doi:10.1007/978-1-4419-9106-5
[18]	Y. Omura, S. Nakashima and K. Izumi, “Investigation on High-Speed Performance of 0.1-μm-Gate, Ultrathin-Film CMOS/SIMOX,” IEICE Transactions on Electronics, Vol. E75-C, No. 12, 1992, pp. 1491-1497.
[19]	Y. Omura, S. Nakashima, K. Izumi and T. Ishii, “0.1-μm Gate, Ultrathin-Film CMOS Devices Using SIMOX Substrate with 80-nm-Thick Buried Oxide Layer,” IEEE Transactions on Electron Devices, Vol. 40, No. 5, 1993, pp. 1019-1022. doi:10.1109/16.210214
[20]	J. R. Brews, “A Charge-Sheet Model for the MOSFET,” Solid State Electronics, Vol. 21, No. 2, 1978, pp. 345-355. doi:10.1016/0038-1101(78)90264-2
[21]	Y. Sakurai, A. Matsuzawa and T. Dozeki, Eds., “Fully Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications,” Springer, Berlin, 2006.