FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

Hassen Loukil, Imen Werda, Nouri Masmoudi, Ahmed Ben Atitallah, Patrice Kadionik

.

DOI: 10.4236/cs.2010.11004                

Abstract

In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.

Keywords

Nios H.264, FPGA, Intra 16 × 16, NIOS-II, SOPC Design

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	T. Wiegand, G. J. Sullivan, G. Bj?ntegaard and A. Luthra, “Overview of the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, 2003, pp. 560576.
[2]	A. Luthra, G. J. Sullivan and T. Wiegand, “Introduction to the Special Issue on the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 13, No. 7, 2003, pp. 557559.
[3]	I. Richardson, “H.264 and MPEG4 Video Compression,” John Wiley and Sons Ltd., Chichester, 2003.
[4]	Joint Video Team (JVT) of ITUT VCEG and ISO/IEC MPEG, “Draft ITUT Recommendation and Final Draft International Standard of Joint Video Specification (ITUT Rec. H.264 and ISO/IEC 1449610 AVC),” May 2003.
[5]	G. J. Sullivan and T. Wiegand, “Video Compression― from Concepts to the H.264/AVC Standard,” Proceedings of the IEEE, Vol. 93, No. 1, 2005, pp. 1831.
[6]	Y.W. Huang, B.Y. Hsieh, T.C. Chen and L. G. Chen, “Analysis, Fast Algorithm, and VLSI Architecture Design for H.264/AVC Intra Frame Coder,” IEEE Transactions Circuit and Systems for Video Technology, Vol. 15, No. 3, 2005, pp. 378401.
[7]	?. Hamzao?lu, ?. Ta?dizen and E. ?ahin, “An Efficient H.264 Intra Frame Coder System Design,” IEEE Transactions on Consumer Electronics, Vol. 54, No. 4, 2008, pp. 19031911.
[8]	K. Suh, S. Park and H. Cho, “An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder,” ETRI Journal, Vol. 27, No. 5, 2005, pp. 511524.
[9]	B. Meng, O. C. Au, C.W. Wong and H.K. Lam, “Efficient IntraPrediction Mode Selection for 4 × 4 Blocks in H.264,” Proceedings of International Conference on Multimedia and Expo, Baltimore, 2003, pp. 521524.
[10]	F. Pan, X. Lin, S. Rahardja, K. P. Lim, Z. G. Li, D. Wu and S. Wu, “Fast Mode Decision Algorithm for Intra prediction in H.264/AVC Video Coding,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 15, No. 7, 2005, pp. 813822.
[11]	B. Meng, O. C. Au, C. W. Wong and H. K. Lam, “Effi cient IntraPrediction Algorithm in H.264,” Proceedings of International Conference on Image Processing, Barcelona, 2003, pp. 837840.
[12]	S. S. Chun, J.C. Yoon and S. Sull, “Efficient Intra Prediction Mode Decision for H.264 Video,” Lecture Notes in Computer Science, Vol. 3767, 2005, pp. 168178.
[13]	H. Loukil, A. Ben Atitallah and N. Masmoudi, “An Efficient FPGA Parallel Architecture for H.264/AVC Intra Prediction Algorithm,” Proceeding of International Conference on Embedded Systems and Critical Applications, Gammarth, Tunisia, 2008, pp. 191196.
[14]	A. Kessentini, B. Kaanich, I. Werda, A. Samet and N. Masmoudi, “Low Complexity Intra 16 × 16 Prediction for H.264/AVC,” Proceedings of International Conference on Embedded Systems & Critical Applications, Tunis, Tunisia, 2008, pp. 197201.
[15]	T.C. Wang, Y.W. Huang, H.C. Fang and L.G. Chen, “Parallel 4 × 4 2D Transform and Inverse Transform Architecture for MPEG4 AVC/H.264,” Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, 2003, pp. 800803.
[16]	L. Liu, Q. Lin, M. Rong and J. Li, “A 2D Forward/In verse Integer Transform Processor of H.264 Based on HighlyParallel Architecture,” Proceedings of the 4th IEEE International Workshop on SystemonChip for RealTime Applications, Banff, Canada, July 1921, 2004, pp. 158161.
[17]	K.H. Chen, J.I. Guo and J.S. Wang, “An Efficient Direct 2D Transform Coding IP Design for MPEG4 AVC/H.264,” IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 2326, 2005, pp. 4517 4520.
[18]	G. Raja, S. Khan and M. J. Mirza, “VLSI Architecture & Implementation of H.264 Integer Transform,” The 17th International Conference on Microelectronics, Islamabad, Pakistan, December 1315, 2005, pp. 218223.
[19]	C.P. Fan, “Fast 2Dimensional 4 × 4 Forward Integer Transform Implementation for H.264/AVC,” IEEE Trans actions on Circuits and Systems—II: Express Briefs, Vol. 53, No. 3, 2006, pp. 174177.
[20]	R. Kordasiewicz and S. Shirani, “Hardware Implemen tation of the Optimized Transform and Quantization Blocks of H.264,” IEEE Canadian Conference on Electrical and Computer Engineering, Canada, May 25, 2004, pp. 943946.
[21]	H. Loukil, S. Arous, I. Werda, A. Ben Atitallah, P. Kadionik and N. Masmoudi, “Hardware Architecture for H.264/ AVC INTRA 16 × 16 Frame Processing,” IEEE International MultiConference on Systems, Signals and Devices, Djerba, Tunisia, March 2326, 2009, pp. 15
[22]	“JVT H.264 Reference Software Version JM10.1,” http:// iphome.hhi.de/suehring/tml/download/old_jm/