has been cited by the following article(s):
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[1]
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Implementation of New Architecture for low leakage-low power-low area and robust SRAM celldesign for computer and communication applications
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VLSI Design
NULL |
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[2]
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Leakage Current Stability Analysis for Subthreshold SRAM
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Electronics,
2022 |
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[3]
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Physical Proximity Verification based on Physical Unclonable Functions
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Thesis,
2018 |
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[4]
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Design of a Low Power 8T SRAM Cell with Improved Stability
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2018 |
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[5]
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Testing of Embedded SRAMs Using Parasitic Extraction Method
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9th International Conference on Robotic, Vision, Signal Processing and Power Applications,
2017 |
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[6]
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An analysis of novel 12T SRAM cell with ımproved read stability
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Int. J. Innov. Res. Eng. Appl. Sci,
2017 |
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[7]
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AN ANALYSIS OF NOVEL 12T SRAM CELL WITH IMPROVED READ STABILITY
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International Journal of Innovative Research in Engineering and Applied Sciences,
2017 |
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[8]
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Low Leakage Asynchronous PP based Single Ended 8T SRAM bit-cell at 45nm CMOS Technology
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2016 |
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[9]
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Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology
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International journal of computer applications,
2013 |
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[10]
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Low-Power SRAM Cell at Deep Sub-Micron CMOS Technology for Multimedia Applications.
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S Birla, NK Shukla, K Sharma, RK Singh, M Pattanaik,
2012 |
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[11]
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A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell
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Electronic System Design (ISED), 2012 International Symposium on. IEEE,
2012 |
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[12]
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Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications
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ACSIT International Journal of Engineering and Technology? ,
2011 |
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[1]
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A Novel Approach for Dynamic Power Reduction in SRAM Cache Memory Bit-Cell at Deep Sub-Micron CMOS Technology
2023 World Conference on Communication & Computing (WCONF),
2023
DOI:10.1109/WCONF58270.2023.10235031
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[2]
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Leakage Current Stability Analysis for Subthreshold SRAM
Electronics,
2022
DOI:10.3390/electronics11081196
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[3]
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9th International Conference on Robotic, Vision, Signal Processing and Power Applications
Lecture Notes in Electrical Engineering,
2017
DOI:10.1007/978-981-10-1721-6_6
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[4]
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A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell
2012 International Symposium on Electronic System Design (ISED),
2012
DOI:10.1109/ISED.2012.55
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