Harmonic Minimization in Seven Level Cascaded Multilevel Inverter Using Selective Harmonic Elimination PWM Techniques

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.org/journal/cs
E-mail: cs@scirp.org

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"Harmonic Minimization in Seven Level Cascaded Multilevel Inverter Using Selective Harmonic Elimination PWM Techniques"
written by V. R. Velmurugan, Jeyabharath Rajaiah, Veena Parasunath,
published by Circuits and Systems, Vol.7 No.14, 2016

has been cited by the following article(s):

[1]	Komparasi Multilevel Inverter Satu Fasa
	2019

[2]	On Approach to Optimize Manufacturing of Bipolar Heterotransistors Framework Circuit of a Seven Level Cascaded Inverter to Increase Their Integration Rate …
	Advanced Science, Engineering and Medicine, 2017

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