"Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs"
written by Saurabh Chaudhury, Anirban Dutta,
published by Circuits and Systems, Vol.2 No.3, 2011
has been cited by the following article(s):
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[11] BDD Ordering and Minimization Using Various Crossover Operators in Genetic Algorithm
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[14] New multiplexer-based switching circuits synthesis methods
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[15] Implementation of Evolutionary Algorithms for BDD Mapped Circuits To Improve Performance Parameters
[16] Performance Comparison among different Evolutionary Algorithms in terms of Node Count Reduction in BDDs
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[17] Binary decision diagram optimization method based on multiplexer reduction methods
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[18] BDD Ordering: A Method to Minimize BDD Size by Using Improved Initial Order
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[19] Implementation Of Hybrid Evolutionary Algorithm For Bdd Optimization By Finding Optimum Variable Ordering
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[20] Implementation Of Reduced Ordered Binary Decision Diagram For Feature Optimization
[21] Implementation of an Improved Initial Order in Various Dynamic Variable Ordering Techniques for BDDs
[22] Ordering and reduction of BDDs for multi-input adders using evolutionary algorithm
[23] Genetic algorithm for ordering and reduction of BDDs for MIMO circuits