New Hybrid Digital Circuit Design Techniques for Reducing Subthreshold Leakage Power in Standby Mode

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"New Hybrid Digital Circuit Design Techniques for Reducing Subthreshold Leakage Power in Standby Mode"
written by Manish Kumar, Md. Anwar Hussain, Sajal K. Paul,
published by Circuits and Systems, Vol.4 No.1, 2013

has been cited by the following article(s):

[1]	Design of Low Power and High-Speed CMOS Phase Frequency Detector for a PLL
	2019

[2]	LECTOR incorporated differential cascode voltage swing logic (L-DCVSL)
	2019

[3]	Dynamic Power Dissipation Analysis in CMOS VLSI Circuit Design with Scaling Down in Technology.
	Journal of Active & Passive Electronic Devices, 2017

[4]	Delay and Energy Efficiency Analysis of a 1-bit CMOS Full Adder.
	Journal of Active & Passive Electronic Devices, 2016

[5]	Delay and Energy Efficiency Analysis of a 1-bit CMOS Full Adder
	2016

[6]	Investigation of Leakage Power in DCVS Logic Family
	2016

[7]	Effective Control of Threshold Voltage of MOS Transistors
	2015

[8]	Analysis and Comparison of Leakage Power Reduction Techniques in CMOS circuits
	2015

[9]	A new low-power 10T SRAM cell with improved read SNM
	International Journal of Electronics, 2015

[10]	MULTITHRESHOLD CMOS SLEEP STACK AND LOGIC STACK TECHNIQUE FOR DIGITAL CIRCUIT DESIGN
	2015

[11]	OIV-CMOS: A novel approach towards leakage power reduction
	2015

[12]	Effective Control of Threshold Voltage of MOS Transistors.
	2015

[13]	POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT
	Journal of Circuits, Systems, and Computers, 2014

[1]	Advances in Signal Processing and Communication Lecture Notes in Electrical Engineering, 2019 DOI:10.1007/978-981-13-2553-3_51

[2]	LECTOR incorporated differential cascode voltage swing logic (L-DCVSL) Analog Integrated Circuits and Signal Processing, 2019 DOI:10.1007/s10470-019-01466-2

[3]	Revisited Design of Short-pulse Power Gated Approach of Subthreshold Leakage Reduction Technique in Combinational Circuits 2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA), 2018 DOI:10.1109/ICSCAN.2018.8541204

[4]	Sleepy CMOS-Sleepy Stack (SC-SS): A Novel High Speed, Area and Power Efficient Technique for VLSI Circuit Design Journal of Circuits, Systems and Computers, 2018 DOI:10.1142/S0218126619501974

[5]	A new low-power 10T SRAM cell with improved read SNM International Journal of Electronics, 2015 DOI:10.1080/00207217.2014.984642

[6]	Analysis and comparison of leakage power reduction techniques in CMOS circuits 2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN), 2015 DOI:10.1109/SPIN.2015.7095351

[7]	OIV-CMOS: A novel approach towards leakage power reduction 2015 International Conference on Computer and Computational Sciences (ICCCS), 2015 DOI:10.1109/ICCACS.2015.7361132

[8]	POWER GATING TECHNIQUE USING FinFET FOR MINIMIZATION OF SUB-THRESHOLD LEAKAGE CURRENT Journal of Circuits, Systems and Computers, 2014 DOI:10.1142/S0218126614501096

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