has been cited by the following article(s):
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[1]
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1.5 bit-per-stage 8-bit Pipelined CMOS A/D Converter for Neuromophic Vision Processor
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2017 |
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[2]
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A/D Converter Architectures for Energy-Efficient Vision Processor
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2017 |
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[3]
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Realization of a 1.5 bits/stage pipeline ADC using switched capacitor technique
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2016 |
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[4]
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Digitally assisted low-power pipelined analog-to-digital converters
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Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW), 2015 IEEE NW Russia,
2015 |
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[5]
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РАЗРАБОТКА МОДЕЛИ КОНВЕЙЕРНОГО АЦП С УЧЕТОМ НЕИДЕАЛЬНОСТИ ОУ В СРЕДЕ LABVIEW
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2015 |
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[6]
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Методы калибровки и коррекции аналого-цифровых преобразователей (обзор)
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2014 |
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[7]
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Methods of calibration and correction of analog-to-digital converters (review)
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Russian Microelectronics, Springer,
2014 |
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[8]
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METODY KALIBROVKI I KORREKTsII ANALOGO-TsIFROVYKh PREOBRAZOVATELEI (OBZOR)
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AS Korotkov - Mikroelektronika, 2014,
2014 |
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[9]
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Calibration and correction methods for analog-to-digital converters: State of the art
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Signals, Circuits and Systems (ISSCS), 2013 International Symposium on. IEEE, 2013.,
2013 |
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[1]
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A new ripple carry adder structure based on a swing‐boosted full adder for concurrent error correction in low‐resolution pipeline analog‐to‐digital converters
International Journal of Circuit Theory and Applications,
2024
DOI:10.1002/cta.3980
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[2]
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Realization of a 1.5 bits/stage pipeline ADC using switched capacitor technique
2016 International Conference on Intelligent Control Power and Instrumentation (ICICPI),
2016
DOI:10.1109/ICICPI.2016.7859675
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[3]
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Digitally assisted low-power pipelined analog-to-digital converters
2015 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW),
2015
DOI:10.1109/EIConRusNW.2015.7102273
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[4]
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Calibration and correction methods for analog-to-digital converters: State of the art
International Symposium on Signals, Circuits and Systems ISSCS2013,
2013
DOI:10.1109/ISSCS.2013.6651256
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