Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
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Citations

"Improved Evaluation Method for the SRAM Cell Write Margin by Word Line Voltage Acceleration"
written by Hiroshi Makino, Naoya Okada, Tetsuya Matsumura, Koji Nii, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda,
published by Circuits and Systems, Vol.3 No.3, 2012

has been cited by the following article(s):

[1]	Low Leakage Variation SRAM Cell with Improved Stability for IOT Applications
	2022

[2]	Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications
	2021

[3]	一種具環繞式閘極與超薄通道之新穎場效電晶體及其模擬分析
	臺灣成功大學學位論文, 2018

[4]	Bias temperature instability ageing-resilient digital system design
	2018

[5]	Cache Power Optimization Using Multiple Voltage Supplies to Exploit Read/Write Asymmetry
	2017

[6]	An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies
	Microelectronics Reliability, 2016

[1]	9T SRAM Cell Based Wired-OR Logic Arrays for Tsetlin Machine Inference 2024 International Symposium on the Tsetlin Machine (ISTM), 2024 DOI:10.1109/ISTM62799.2024.10931372

[2]	Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications Journal of Circuits, Systems and Computers, 2021 DOI:10.1142/S0218126621502704

[3]	An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies Microelectronics Reliability, 2016 DOI:10.1016/j.microrel.2016.07.154

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