On the Production Testing of Memristor Ratioed Logic (MRL) Gates - Circuits and Systems

CS > Vol.7 No.10, August 2016

On the Production Testing of Memristor Ratioed Logic (MRL) Gates ()

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Download as PDF (Size: 1016KB) PP. 3016-3025

DOI: 10.4236/cs.2016.710257 1,608 Downloads 3,179 Views Citations

Author(s)

Ahmed Shukry Emara¹, Ahmed Hassan Madian², Hassanein Hamed Amer¹, Sherif Hassanein Amer¹, Mohamed Bakr Abdelhalim³

Affiliation(s)

¹Electronics and Communications Engineering, The American University in Cairo, Cairo, Egypt.
²Radiation Energy Department, Egyptian Atomic Energy Authority, Cairo, Egypt.
³College of Computing and Information Technology AASTMT, Cairo, Egypt.

ABSTRACT

This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. Test escapes may take place while testing faults in the memristors. Therefore, two solutions are proposed to obtain full coverage for the MRL NAND and NOR gates. The first is to apply scaled input voltages and the second is to change the switching threshold of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs.

KEYWORDS

Memristors, MRL, Production Testing, Fault Model, Fault Coverage

Share and Cite:

Emara, A. , Madian, A. , Amer, H. , Amer, S. and Abdelhalim, M. (2016) On the Production Testing of Memristor Ratioed Logic (MRL) Gates. Circuits and Systems, 7, 3016-3025. doi: 10.4236/cs.2016.710257.

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