Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique - Circuits and Systems

CS > Vol.7 No.9, July 2016

Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique ()

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Download as PDF (Size: 554KB) PP. 2593-2602

DOI: 10.4236/cs.2016.79224 2,133 Downloads 4,722 Views Citations

Author(s)

S. K. Manikandan¹, C. Palanisamy²

Affiliation(s)

¹Department of EEE, Velalar College of Engineering and Technology, Erode, India.
²Department of Information Technology, Bannari Amman Institute of Technology, Sathyamangalam, India.

ABSTRACT

Vedic mathematics is the system of mathematics followed in ancient Indian and it is applied in various mathematical branches. The word “Vedic” represents the storehouse of all knowledge. Because using Vedic Mathematics, the arithmetical problems are solved easily. The mathematical algorithms are formed from 16 sutras and 13 up-sutras. But there are some limitations in each sutra. Here, two sutras Nikhilam sutra and Karatsuba algorithm are considered. In this research paper, a novel algorithm for binary multiplication based on Vedic mathematics is designed using bit reduction technique. Though Nikhilam sutra is used for multiplication, it is not used in all applications. Because it is special in multiplication. The remainder is derived from this sutra by reducing the remainder bit size to N-2 bit. Here, the number of bits of the remainder is constantly maintained as N-2 bits. By using Karatsuba algorithm, the overall structure of the multiplier is designed. Unlike the conventional Karatsuba algorithm, the proposed algorithm requires only one multiplier with N-2 bits only. The speed of the proposed algorithm is improved with balancing the area and the power. Even though there is a deviation in lower order bits, this method shows larger difference in higher bit lengths.

KEYWORDS

Karatsuba, Nikhilam Sutra, Bit Reduction, Remainder, Multipliers

Share and Cite:

Manikandan, S. and Palanisamy, C. (2016) Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique. Circuits and Systems, 7, 2593-2602. doi: 10.4236/cs.2016.79224.

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