FSM Based DFS Link for Network on Chip - Circuits and Systems

CS > Vol.7 No.8, June 2016

FSM Based DFS Link for Network on Chip ()

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Download as PDF (Size: 1566KB) PP. 1734-1750

DOI: 10.4236/cs.2016.78150 1,656 Downloads 2,632 Views

Author(s)

Erulappan Sakthivel¹, Veluchamy Malathi², Muruganantham Arunraja¹, Govinndaraj Perumalvignesh¹

Affiliation(s)

¹Electrical and Electronics Engineering, The Siliconharvest, Madurai, India.
²Electrical and Electronics Engineering, Anna University Regional Campus, Madurai, India.

ABSTRACT

As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMCCMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work.

KEYWORDS

Network-on-Chip (NoC), Dynamic Frequency Scaling (DFS), Finite State Machines (FSM)

Share and Cite:

Sakthivel, E. , Malathi, V. , Arunraja, M. and Perumalvignesh, G. (2016) FSM Based DFS Link for Network on Chip. Circuits and Systems, 7, 1734-1750. doi: 10.4236/cs.2016.78150.

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