Author(s)

Aakansha Suchitta^1,2, Richa Srivastava^1,3*, Akanksha Dewaker^1,4, Maneesha Gupta¹

¹Netaji Subhas Institute of Technology, New Delhi, India.
²Present Address: Indian Institute of Technology Delhi (IIT-D), New Delhi, India.
³Present Address: A.K.G. Engineering College, Ghaziabad, India.
⁴Present Address: TRAI, New Delhi, India.

This paper proposes novel floating-gate MOSFET (FGMOS) based Voltage Buffer, Analog Inverter and Winner-Take-All (WTA) circuits. The proposed circuits have low power dissipation. All proposed circuits are simulated using SPICE in 180 nm CMOS technology with supply voltages of ±1.25 V. The simulation results demonstrate increase in input range for FGMOS based voltage buffer and analog inverter and maximum power dissipation of 0.5 mW, 1.9 mW and 0.429 mW for FGMOS based voltage buffer, analog inverter and WTA circuits, respectively. The proposed circuits are intended to find applications in low voltage, low power consumer electronics.

FGMOS, Voltage Buffer, Analog Inverter, Winner-Take-All (WTA), Analog Signal Processing Circuits

Suchitta, A. , Srivastava, R. , Dewaker, A. and Gupta, M. (2016) Design of Low-Voltage, Low-Power FGMOS Based Voltage Buffer, Analog Inverter and Winner-Take-All Analog Signal Processing Circuits. Circuits and Systems, 7, 1-10. doi: 10.4236/cs.2016.71001.