Author(s)

Kenichi Ohhata, Wataru Yoshimura, Daiki Tabira, Futoshi Shimozono, Masataro Iwamoto

Department of Electrical and Electronics Engineering, Graduate School of Science and Engineering, Kagoshima University, Kagoshima, Japan.

A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.

Analog-to-Digital Convertor; Subranging Architecture; Resistor Ladder; Foreground Calibration; Offset Drift

Ohhata, K. , Yoshimura, W. , Tabira, D. , Shimozono, F. and Iwamoto, M. (2014) A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration. Circuits and Systems, 5, 76-88. doi: 10.4236/cs.2014.54010.