Prof. Samar K. Saha

Electrical Engineering Department 

Santa Clara University, USA

Adjunct Professor

Email: samar@ieee.org, samarsah@pacbell.net

Qualifications

1992 MSEM, Stanford University, USA, Engineering Management

1981 Ph.D., Gauhati University, India, Solid State Physics

1973 M.Sc., Gauhati University, India, Physics

1971 B.Sc., Cotton College, India, Physics (Honors)

Publications (Selected)

1. Saha, S.K. (2015), Compact models for integrated circuit design: Conventional transistors and beyond: CRC Press, Taylor & Francis group, London. 
2. Saha, S.K. (2014), “Compact MOSFET modeling for process variability-aware VLSI circuit design,” IEEE Access, vol. 2, pp. 103–105. 
3. Saha S.K. (2013), “Introduction to technology CAD,” in Technology Computer Aided Design: Simulation for VLSI MOSFET, C.K. Sarkar (ed.): CRC Press, Taylor & Francis group, London. 
4. Saha S.K. (2012), “Non-linear coupling voltage of split-gate flash memory cells with additional top coupling gate,” IET Circuits, Devices & Systems, vol. 6, no. 3, pp. 204–210. 
5. Saha S.K. (2010), “Modeling the effectiveness of computer-aided technology development projects in the semiconductor industry,” Int. J. of Engineering Management and Economics, vol. 1, no. 2/3, pp. 162–178. 
6. Saha S.K. (2010), “Modeling process variability in scaled CMOS technology,” IEEE Design & Test of Computers, vol. 27, no. 2, pp. 8–16. 
7. Saha S.K. (2008), “Scaling considerations for sub-90 nm split-gate Flash memory cells,” IET Circuits, Devices & Systems, vol. 2, no. 1, pp. 144–150. 
8. Saha S.K. (2007), “Design considerations for sub-90 nm split-gate Flash memory cells,” IEEE Trans. Electron. Devices, vol. 54, no. 11, pp. 3049–3055. 
9. Saha S. (2001), “Scaling considerations for high performance 25 nm metal-oxide-semiconductor field-effect transistors,” J. Vac. Sci. Tech. B, vol. 19, no. 6, pp. 2240-2246. 
10. Saha S. (2001), “Design considerations for 25 nm MOSFET devices,” Solid-State Electron., vol. 45, no. 10, pp. 1851-1857. 
11. Saha S. (1999), “Managing technology CAD for competitive advantage: an efficient approach for integrated circuit fabrication technology development,” IEEE Trans. Eng. Manage., vol. EM-46, no. 2, pp. 221–229. 
12. Saha S. (1998), “Effects of inversion layer quantization on channel profile engineering for nMOSFETs with 0.1 µm channel lengths,” Solid-State Electron., vol. 42, no. 11, pp. 1985–1991. 
13. Saha S. (1995), “MOSFET test structures for two-dimensional device simulation,” Solid-State Electron., vol. 38, no. 1, pp. 69–73. 
14. Saha S. (1994), “Extraction of substrate current model parameters from device simulation,” Solid-State Electron., vol. 37, no. 10, pp. 1786–1788. 
15. Saha S., Yeh C.S. and Gadepally, B. (1993), “Impact ionization rate of electrons for accurate simulation of substrate current in submicron devices,” Solid-State Electron., vol. 36, no. 10, pp. 1429–1432. 
16. Galvan D.H., Saha S.K. and Henneberger W.C. (1983), “A simple algorithm for Clebsch-Gordan coefficients,” Am. J. Phys., vol. 51, no. 10, p. 953. 
17. Saha S.K. (1982), “Temperature dependent electrical resistivity of evaporated bismuth film,” Phys. Stat. Solidi (a), vol. 71, no. 2, pp. K173–K175. 
18. Saha S.K. (1981), “Lattice distortion spectrum of evaporated antimony,” Indian Journal of Pure & Appl. Phys., vol. 19, no. 6, pp. 577-578. 
19. Saha S.K. (1981), “Effects of annealing on the electrical resistance of vacuum deposited tellurium films,” Indian Journal of Pure & Appl. Phys., vol. 19, no. 2, pp. 111-114. 
20. Saha S.K. and Mahanta P.C. (1980), “Lattice distortion spectrum of evaporated bismuth films,” Indian Journal of Pure & Appl. Phys., vol. 18, pp. 159-161.